In the art of DVD system that utilizes, for example, a DVD player, a DVD-R, and a DVD-RW, it is necessary to provide a multiplicity of clocks of different reference frequencies (referred to as reference frequency clocks), including at least a 27 MHz clock series (first reference frequency series) for a video system, a 33.8688 MHz clock series (second reference frequency series) for a sound system (particularly CD) (the series including integral multiples of a sampling frequency of 44.1 kHZ), and a 36.864 kHz clock series (third reference frequency series) for another sound system (particularly DVD) (the series including integral multiples of 48 kHz and 32 kHz sampling frequencies).
These three reference frequency series can be obtained using individual oscillation modules. However, this approach is costly for a clock generation system because it requires one oscillation module for each of the required reference clock frequencies. Then, in order to reduce the cost, one might consider to generate two of the three reference frequency series from the remaining one, utilizing PLL (phase-locked loop) circuits, as shown in FIG. 7. FIG. 7 shows a clock generation system conjectured by the inventor in the process of devising the present invention, which is shown as a reference, but not prior art.
In the system shown in FIG. 7, a first reference frequency clock Fr1 (27 MHz) generated by an oscillation module is used as the basis for generating the remaining two reference frequency clocks, that is a second reference frequency clock Fr2 (33.8688 MHz) and a third reference frequency clock Fr3 (36.864 MHz).
In the first PLL circuit 70a as shown in FIG. 7, the first 27 MHz reference frequency clock Fr1 is supplied to a first frequency divider 71a, which frequency-divides the input first clock by a factor of 625 and supplies it to one comparison input terminal P1 of a phase comparator (PD) 73a. The second frequency divider 72a receives the output of the PLL circuit 70a and frequency-divides it by a factor of 3136, which is supplied to a PD 73a as another comparison input P2. The PD 73a compares the two inputs P1 and P2 and generates an output (referred to as comparison output) indicative of the phase difference between them. The comparison output is smoothed by a low-pass filter (LPF) before it is supplied to a voltage control oscillator (VCO) 75a as a control signal. The VCO 75a changes its oscillation frequency according to the control signal input so that the two inputs to the PD 73a coincide in frequency and in phase. The loop gain of this PLL circuit is large, so that remaining deviation is extremely small. Thus, the frequency of the output of the VCO 75a is converted to 135.4752 (=27×3136/625) MHz, in accordance with the frequency division ratio of the frequency dividers 71a and 72a. 
The output frequency of the VCO 75a is frequency-divided by a frequency divider 76a by a factor of 4, generating a second reference frequency clock Fr2. The output frequency of the VCO 75a is further frequency-divided by a 1/6 frequency divider 77a, a 1/8 frequency divider 78a, and a 1/12 frequency divider 79a, respectively, into 22.5792 MHz, 16.9344 MHz, and 11.2896 MHz. These frequencies have specific relationships with the second reference frequency clock Fr2. These clocks belonging to the second reference frequency series have integral multiple of the sampling frequency of 44.1 kHz for use with CD systems.
The second PLL circuit 70b also performs frequency division similar to that of the first PLL circuit 70a, except that the frequency division ratio of the first frequency divider 71b is 1/375, while that of the second frequency divider 72b is 1/2048. The output frequency of the VCO 75b is converted into 147.456(=27×2048/375) MHz in accordance with the division ratios of the frequency dividers 71b and 72b. Incidentally, reference numeral 73b indicates a PD, and 74b indicates an LPF.
The output frequency of the VCO 75b is frequency-divided by the frequency divider 76b by a factor of 4 to produce a third reference frequency clock Fr3. Additionally, the output frequency of the VCO 75b is frequency-divided by a 1/6 frequency divider 77b, a 1/8 frequency divider 78b, and a 1/12 frequency divider 79b to generate frequencies of 24.576 MHz, 18.432 MHz, and 12.288 MHz, respectively, which have specific frequency relationship with the third reference frequency clock Fr3. The frequencies of these clocks belonging to the third reference frequency series Fr3s are integral multiples of audio sampling frequencies 48 kHz and 32 kHz in DVD systems.
Clocks of a first reference frequency series Fr1s are also generated. The series includes the first reference frequency clock Fr1 (27 MHz) and a clock of 13.5 MHz obtained by frequency division of the first reference frequency clock Fr1 by a 1/2 frequency divider 76d. 
Thus, one may choose necessary frequency clocks from the first through third reference frequency series Fr1s–Fr3s for his use.
The S/N (signal-to-noise) ratios of the clocks generated by the clock generation system shown in FIG. 7 can be obtained based on a known S/N theory as follows. As an example, S/N ratio of clocks of the second reference frequency series Fr2s will be discussed. It will be understood that by the frequency division of the first reference frequency clock Fr1 by a factor of 625, the S/N ratio is improved by 20 log 625 [dB]. Hence, theoretically, the S/N ratio of the output signal of the first frequency divider 71a equals (S/N ratio of the output signal+20 log 625) [dB]. Assuming that the S/N ratio of the first reference frequency clock is 80 [dB], it is 80+56=136 [dB]. Note that the S/N ratios are rounded to integers for simplicity. (It is also the case in the following discussion.)
It should be noted, however, that since a PLL circuit is in operation on the noise floor of a given IC (integrated circuit) on which the PLL circuit is formed, the S/N ratio of the PLL circuit is limited by the S/N ratio of the noise floor. The S/N ratio of the noise floor is governed by the fluctuations in the power supply potential, which is on the order of 90 [dB]. Hence, the S/N ratio of the PLL circuit is limited by the S/N ratio of the noise floor (90 [dB]). Hence, the S/N ratio of the output of the first frequency divider 71a, that is, the S/N ratio of one comparison input P1 to the PD 73a is at most 90 [dB].
Since the S/N ratios of the comparison inputs P1 and P2 to the PD 71a are the same, the S/N ratio of the comparison input P2 is 90 [dB]. The S/N ratio of the comparison input to the second frequency divider 72a is lowered by 20log3136 [dB], since the input P2 is stepped up by a factor of 3136. Therefore, the S/N ratio of the input to the second frequency divider 72a becomes (90 (for the comparison input P2) −20log3136) [dB], or 20.3 [dB].
Thus, S/N ratios of clocks of the second reference frequency series Fr2s are 32.3 [dB] for the second reference frequency clock Fr2, 35.8 [dB] for the 22.5792 MHz clock, 38.3 [dB] for the 16.9344 MHz clock, and 41.8 [dB] for the 11.2896 MHz clock.
Similar calculations lead to S/N ratios of the clocks of the third reference frequency series Fr3s. They are: 36.0 [dB] for the third reference frequency clock Fr3; 39.5 [dB] for 24.576 MHz clock; 42.0 [dB] for 18.432 MHz clock; and 45.5 [dB] for 12.288 MHz clock.
In this way, using PLL circuits and frequency dividers as shown in FIG. 7, it is possible to generate clocks of a second reference frequency series Fr2s which include a second reference frequency clock Fr2 obtained by multiplying the frequency of the first reference frequency clock Fr1 by a predetermined ratio, and clocks of a third reference frequency series Fr3s which include a third reference frequency clock Fr3 obtained by a similar multiplication. However, the S/N ratios of the clocks of the second and third reference frequency series are lowered to 30 [dB] −40 [dB]. This deterioration in S/N ratio is a problem that must be solved, since DVD systems, etc. in general requires a S/N ratio of at least 50 [dB], preferably more than 60 [dB].